1. Technical Field
The present invention is directed to data processing systems and more particularly to microprocessors. Still more specifically, the present invention is directed to a method, apparatus, and computer program product for sharing data in a cache among threads in a simultaneous multi-threaded processor.
2. Description of Related Art
A symmetric multiprocessing (SMP) data processing system has multiple processors that are symmetric such that each processor has the same processing speed and latency. An SMP system has one operating system that divides the work into tasks that are distributed evenly among the various processors by dispatching one software thread of work to each processor at a time. Thus, a processor in an SMP system executes only one thread at a time.
A simultaneous multi-threading (SMT) data processing system includes multiple processors that can each concurrently execute more than one thread at a time per processor. An SMT system has the ability to favor one thread over another when both threads are running on the same processor.
Known systems can include a shared processor where the shared processor is shared among the various processes that are being executed by the system. The shared processor can be either an SMP or SMT type of processor.
A shared processor may be part of a logically partitioned system and shared among the various partitions in the system. These systems typically include firmware, also called a hypervisor, that manages and enforces the partitioning and/or sharing of the processor. For example, a hypervisor may receive a request from the system to dispatch a virtual processor to a physical processor. The virtual processor includes a definition of the work to be done by a physical processor as well as various settings and state information that are required to be set within the physical processor in order for the physical processor to execute the work. In known shared processor systems, the hypervisor supervises and manages the sharing of a physical processor among all of the logical partitions.
A multithreaded (SMT) processor fetches data from memory and stores it into a single L1 data cache array. Each thread that is processed by this processor needs to have space allocated to it in the L1 cache. A problem arises when decisions are made as to how to equitably divide the L1 data cache to distribute enough storage space in the cache for each thread's use.
One approach to dividing the cache is to divide the total storage space provided by the L1 cache into two equal pieces that are a fixed static size. In this case the L1 cache is segregated into two areas, each area dedicated to one of the threads. Each thread will have its own dedicated portion of the L1 cache. The size of each piece will not change during while the threads are executing.
This approach may cause the performance of one of the threads to suffer. In cases where a first thread requires a larger storage area in the cache and the other thread does not need its half of the cache, performance of the first thread suffers.
Sharing happens normally in a system environment in the operating system. In these cases, there may be critical variables that both threads will be fetching and could possibly be storing at the same time. In this case, it is desirable to allow the concurrent fetching and/or storing of the data by one thread without invalidating the cache line of the same data being used by the other thread.
In addition, when running multiple copies of the same program for benchmarking, two threads may be using the same effective addresses, but may or may not be using the same real addresses. In this case, if the real addresses are different, it is desirable to avoid thrashing the data cache. Thrashing occurs when two different processes continually insist on having their data occupy the same logical location in the cache. Usually the installed data resides in the location for a minimum time such that only a few elements of the entire data are actually consumed by the process before the data is evicted again by the other process.
Therefore, a need exists for a method, apparatus, and computer program product for sharing data in a cache among threads in a simultaneous multi-threaded processor.